This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application Nos. 2000-247735, 2000-389106 and 2001-180633, filed on Aug. 17, 2000, Dec. 21, 2000 and Jun. 14, 2001, respectively, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly a dynamic semiconductor memory device (DRAM).
2. Related Background Art
In a related DRAM, a memory cell is composed of an MOS transistor and a capacitor. The scale-down of the DRAM has been remarkably advanced by the adoption of a trench capacitor structure and a stacked capacitor structure. At present, the cell size of a unit memory cell is scaled down to an area of 2 Fxc3x974 F=8 F2, where F is a minimum feature size. Namely, the minimum feature size F decreases with the advance of generation, and when the cell size is generally taken to be xcex1F2, a coefficient xcex1 also decreases with the advance of generation. Thus, at the present of F=0.18 xcexcm, xcex1=8 is realized.
In order to hereafter secure the trend of cell size or chip size which is the same as before, it is demanded to satisfy xcex1 less than 8 in F less than 0.18 xcexcm and further satisfy xcex1 less than 6 in F less than 0.13 xcexcm, and together with microfabrication, the formation of cell size of the possible small area becomes a large problem. Accordingly, various proposals for decreasing the size of the one memory cell with the one transistor and one capacitor to 6F2 or 4F2 are made. However, practical use is not easy since there are a technical difficulty that the transistor has to be a vertical type, a problem that electric interference between adjacent memory cells increases, and in addition difficulties in terms of manufacturing technology including fabrication, film formation, and the like.
On the other hand, some proposals for a DRAM in which a memory cell is composed of one transistor without using a capacitor are made as mentioned below.
(1) JOHN E. LEISS et al, xe2x80x9cdRAM Design Using the Taper-Isolated Dynamic Cellxe2x80x9d (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4, APRIL 1982, pp707-714)
(2) Japanese Patent Laid-open Publication No. H3-171768
(3) Marnix R. Tack et al, xe2x80x9cThe Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperaturesxe2x80x9d (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL, 37, MAY, 1990, pp1373-1382)
(4) Hsing-jen Wann et al, xe2x80x9cA Capacitorless DRAM Cell on SOI Substratexe2x80x9d (IEDM93, pp635-638)
A memory cell in (1) is composed of MOS transistors, each of which has a buried channel structure. Charge and discharge to/from a surface inversion layer is performed using a parasitic transistor formed at a taper portion of an element isolation insulating film to perform binary storage.
A memory cell in (2) uses MOS transistors which are well-isolated from each other and uses a threshold voltage of the MOS transistor fixed by a well potential as binary data.
A memory cell in (3) is composed of MOS transistors on an SOI substrate. A large negative voltage is applied from the SOI substrate side, and by utilizing accumulation of holes in an oxide film of a silicon layer and an interface, binary storage is performed by emitting and injecting these holes.
A memory cell in (4) is composed of MOS transistors on an SOI substrate. The MOS transistor is one in terms of structure, but here a structure, in which a reverse conduction-type layer is formed on top of the surface of a drain diffusion region, whereby a P-MOS transistor for write and an N-MOS transistor for read are substantially combined integrally, is adopted. With a substrate region of the N-MOS transistor as a floating node, binary data are stored by its potential.
However, in (1), the structure is complicated and the parasitic transistor is used, whereby there is a disadvantage in the controllability of its characteristic. In (2), the structure is simple, but it is necessary to control potential by connecting both a drain and a source of the transistor to a signal line. Moreover, the cell size is large and rewrite bit by bit is impossible because of the well isolation. In (3), a potential control from the SOI substrate side is needed, and hence the rewrite bit by bit is impossible, whereby there is a difficulty in controllability. In (4), a special transistor structure is needed, and the memory cell requires a word line, a write bit line, a read bit line, and a purge line, whereby the number of signal lines increases.
An object of the present invention is to provide a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines and a method of manufacturing the same.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device including at least one transistor, wherein the transistor comprises:
a semiconductor layer which is a first conduction type and electrically isolated from other memory cells to get floating;
a drain diffusion region which is a second conduction type, formed in the first conduction-type semiconductor layer, and connected to a bit line;
a source diffusion region which is the second conduction type, formed apart from the drain diffusion region in the first conduction-type semiconductor layer, and connected to a source line; and
a gate electrode which is formed on the semiconductor layer between the drain diffusion region and the source diffusion region with a gate insulator therebetween, and connected to a word line;
wherein the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the semiconductor layer and a second data state having a second threshold voltage in which the excessive majority carriers in the semiconductor layer are emitted.
According to another aspect of the present invention, a semiconductor memory device comprising:
an SOI substrate in which a silicon layer is formed on an insulating film formed on a silicon substrate;
a plurality of transistors formed in the silicon layer, pairs of transistors, each pair sharing a drain diffusion region, being arranged in a matrix form with element-isolated in a channel width direction;
a plurality of word lines each connected to gate electrodes of transistors arranged in a first direction in common;
a plurality of bit lines disposed in a second direction intersecting the first direction and connected to the drain diffusion regions of the transistors;
a common source line formed by continuously disposing source diffusion regions of the transistors arranged in the first direction,
wherein the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the silicon layer and a second data state having a second threshold voltage in which the excessive majority carriers in the silicon layer are emitted.
According to a further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming an insulating film on a semiconductor substrate;
forming a first conduction-type semiconductor layer on the insulating film;
forming a mask having an opening in a gate forming region on the semiconductor layer;
forming a side wall insulating film on a side wall of the opening of the mask;
doping impurities to the semiconductor layer through the opening of the mask to form a first conduction-type impurity region having an impurity concentration higher than the semiconductor layer;
forming a gate insulator and a gate electrode by burying them in the opening of the mask after the side wall insulating film is removed; and
doping impurities to the semiconductor layer to form second conduction-type drain diffusion region and source diffusion region after the mask is removed.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming an insulating film on a semiconductor substrate;
forming a first conduction-type semiconductor layer on the insulating film;
forming a mask having an opening in a gate forming region on the semiconductor layer;
forming a first side wall insulating film on a side wall of the opening of the mask;
doping impurities to the semiconductor layer through the opening of the mask to form a first conduction-type first impurity region having an impurity concentration higher than the semiconductor layer;
forming a gate insulator and a gate electrode by burying them in the opening of the mask after the first side wall insulating film is removed;
doping impurities to the semiconductor layer to form second conduction-type second impurity regions in a drain region and a source region after the mask is removed,
forming a second side wall insulating film on a side wall of the gate electrode, and
doping impurities to the semiconductor layer to form second conduction-type third impurity regions having an impurity concentration higher than the second impurity regions in the drain region and the source region.